The present invention generally relates to a semiconductor storage device such as a dynamic random access memory (DRAM), and more particularly relates a semiconductor storage device with a plurality of memory cells, each including two transistors and a single capacitor. In this specification, a memory cell of this type will be called a "two-transistor/one-capacitor memory cell".
A memory cell widely used as an elementary unit for a semiconductor storage device like a DRAM is a "one-transistor/one-capacitor memory cell" including just one switching transistor and only one capacitor. This is an inevitable consequence of downsizing of memory cells, or reduction in number of components included in a single memory cell. To further downsize the one-transistor/one-capacitor memory cell, various techniques of modifying the shape of, or miniaturizing the size of, a memory cell while ensuring sufficient storage capacity have already been put into practice.
Hereinafter, a conventional one-transistor/one-capacitor memory cell will be described with reference to FIG. 12. FIG. 12 illustrates a planar layout for conventional memory cells. As shown in FIG. 12, a plurality of mutually adjacent memory cells 100A, 100B are arranged on a substrate to form a regular pattern. In the memory cell 100A, for example, an active region 101 is formed out of a diffused layer for a switching transistor. Over the active region 101, a word line 102 is formed as a gate electrode for controlling the switching transistor.
A capacitor (not shown) is formed over the active region 101 on the opposite side to the memory cell 100B across the word line 102. Under the capacitor, a capacitor contact 103 for electrically connecting the storage node of the capacitor to the active region 101 is formed.
Over the active region 101, a bit line contact 104 is also provided in an extended region on the opposite side to the capacitor contact 103 across the word line 102. And a bit line 105 for reading and writing data from/onto the capacitor is formed over a substrate so as to be connected to the bit line contact 104 and to cross the word lines 102.
As can be seen, the conventional one-transistor/one-capacitor memory cells have its planar layout optimized so as to downsize the memory cells 100A and 100B by minimizing the line pitch between adjacent bit lines 105 or word lines 102 and yet to attain sufficient storage capacity.
An integrated circuit has never been implemented using the two-transistor/one-capacitor memory cells, which are the target of the present invention. If the conventional one-transistor/one-capacitor memory cells are simply combined to implement this scheme, then each two-transistor/one-capacitor memory cell requires an area almost four times as large as the conventional memory cell, thus tremendously increasing the area of a chip occupied by the memory cells.
In the two-transistor/one-capacitor memory cell, two switching transistors are commonly connected to a single capacitor for storing data thereon. Accordingly, if one of these switching transistors is dedicated to writing while the other to reading, then the operation cycle can be doubled without changing the frequency of operation clock signals. Thus, the two-transistor/one-capacitor memory cell can easily contribute to high-speed operation in such a case.